MB Lab Technology

Software — mbkicad

KiCad Integration

Let KiCad answer, instead of parsing its files by hand.

In development mbkicad — command line and desktop app

What it does

Drives kicad-cli to run ERC, DRC and schematic parity on a real project, export every fabrication and documentation file KiCad can make, and check a board's layout for the EMC problems that are cheapest to fix while it is still in layout.

  • ERC, DRC and schematic-parity checks with a pass/fail exit code
  • Netlist, BOM, Gerbers, drill, pick-and-place, STEP, PDF, SVG and 3-D renders
  • EMC layout review — ground plane, return path, decoupling, stitching, board edge
  • Readable generated schematics from netlist-as-code, checked against KiCad's own netlist
There is no window to photograph - this application is a command line - so this is the report one run writes. ERC and DRC through KiCad 10 itself rather than re-derived from the files: 28 electrical warnings and no errors, 26 design-rule warnings and no errors, nothing unconnected, and schematic parity clean. The two numbers on the right are its own: 35 EMC errors against 24 warnings, and a layout risk score of 38.5 where 100 would mean nothing found. Every finding carries a stable id, so the same problem keeps the same name between runs.
There is no window to photograph - this application is a command line - so this is the report one run writes. ERC and DRC through KiCad 10 itself rather than re-derived from the files: 28 electrical warnings and no errors, 26 design-rule warnings and no errors, nothing unconnected, and schematic parity clean. The two numbers on the right are its own: 35 EMC errors against 24 warnings, and a layout risk score of 38.5 where 100 would mean nothing found. Every finding carries a stable id, so the same problem keeps the same name between runs.
The EMC layout analysis, which is the part KiCad does not do. Rule RP-001 here is the return path: each of these nets crosses between layers with no ground stitching via within a millimetre of the signal via, so the return current has to find its way around - a loop antenna by accident. The finding names the net, counts the transitions, says which layers, tags whether it matters for radiated emissions, radiated immunity or a near-field probe, and then says in italics what to do about it.
The EMC layout analysis, which is the part KiCad does not do. Rule RP-001 here is the return path: each of these nets crosses between layers with no ground stitching via within a millimetre of the signal via, so the return current has to find its way around - a loop antenna by accident. The finding names the net, counts the transitions, says which layers, tags whether it matters for radiated emissions, radiated immunity or a near-field probe, and then says in italics what to do about it.

Worth knowingFurther from finished than the other two in development. There is no window yet - it is command line only - and no installer, so it cannot be packaged and sent. The Altium conversion named in its brief has not been started.

On video

One recording of it actually running.

A screenshot of a program that moves is only half of it, so here it is moving. It has no window at all - the command line is the product, so this is a session, recorded off the screen. Nothing plays until you press it.

30 s probe first: which KiCad it found, and what the project actually holds - 233 footprints, 121 nets, 1014 tracks and 415 vias on a two-layer 100 by 100 mm board. Then check, which runs ERC, DRC, schematic parity and the EMC layout analysis in one pass. ERC and DRC come back 0 and 0, nothing unconnected, parity clean - and then the EMC analysis returns 1 error and 27 warnings, named net by net: a long clock trace, reference plane gaps under particular signals, and missing stitching vias at layer transitions listed by the net that needs them.

Get in touch

KiCad Integration is still being built, so there is nothing to install yet. Tell me what you would need it to do - what it becomes is shaped partly by the answers to this.

Or email mblab.technology@gmail.com. Your details are used to answer you and to follow up — nothing else.

Requirements

  • Windows 10 or 11, 64-bit
  • About 200 MB of disk
  • No .NET install needed — the runtime is bundled
  • No Excel needed — workbooks are written directly

Also in the set

PCB Test AnalysisWill this board be testable before you cut the fixture?EMC Design CompatibilityFind the emissions failure on your bench, not in a rented chamber.Validation TestingHow many samples, which tests, how long, how much.